The present invention relates to method and device for repairing arrays with redundancy, in which the repair solution for repairing the faults of memory cells by the use of spare cells (lines) is obtained.
Conventionally, when the density of semiconductor memories known as Random Access Memories (RAMs) was not so high, even if some bit faults took place, such inconveniences were overcome by the improvement of the manufacturing conditions etc.
However, as semiconductor memories were increased in capacity, there has come to be developed the technique according to which, not only the elimination of bit faults is intended, but also, on the premise that some bit faults will take place, spare lines are provided for repairing such bit faults (replacing the lines containing the bit faults). It is because, if spare lines are provided, the substantial density is deceased, but, after all, it is advantageous in view of productivity etc.
In case of utilizing this spare technique, first faulty elements are detected by the use of a memory-tester (or a bit fail tester apparatus or the like). Thereafter, the process of determining, which faulty lines are to be repaired, by the use of a predetermined number of spare rows and a predetermined number of spare columns, is performed, taking into consideration constraints, if any on the way of using of the spare lines. In accordance with the result of the above-mentioned process, for instance, a switching address setting fuse provided on the chip is blown out by a laser in the repair apparatus, whereby address of the line to be replaced by each spare is set.
The problematic points of the above-mentioned conventional processing technique will be described in detail. As mentioned above, a semiconductor memory includes, in addition to the essential memory array, spare lines. These spare lines are ordinarily assigned in a state divided and grouped for the respective memory array areas for taking charge of repair. If faulty elements are detected, the lines (rows or columns) containing the faulty elements are decided as faulty lines, so that those lines are replaced by spare lines taking charge of the repair for this area. In this way, until all the faulty elements are repaired by the spare lines, the replacement of the faulty lines with the spare lines is continued. If all the faulty elements can thus be repaired by the spare lines, the repair/replacement of the semiconductor memory turns out to be successful. On the other hand, in case, even if the spare lines were all used, some faulty elements still exist (or in case, even if all the spare lines in a certain area to be repaired thereby were used, faulty elements still exist in the area), it is decided that the faults are unrepairable. As for the above-mentioned repair process, criteria pertaining to an optimum repair method in view of the manufacturing costs, such as for instance the criterion that the number of spare lines used in case the faults are repairable should desirably be minimum, in many cases.
According to the conventional repair methods, in view of the fact that, concerning the establishment of the correspondence between faulty lines and spare lines, it takes a large amount of calculation time if all the combinations thereof are evaluated by calculation, so that there was employed the method according to which, for instance, the spare lines are successively allocated to the faulty lines successively in a manner first allocating a spare line to the line containing largest number of faults, even if all the spare lines are allocated, all the faulty lines are unrepairable, the allocation of the spare lines is changed from the beginning thereof. Or, there was adopted the method according to which the spare lines were successively allocated in such a manner that first a spare line is allocated to the fault column at the left side (or the fault row at the upper side), and, even if all the spare lines were allocated, all the faulty lines could not be repaired, the allocation of the spare lines was changed from the beginning thereof.
However, according to these conventional methods, even in case a relationship of correspondence exists between the repairable faulty lines and the spare lines, all the combinations cannot be confirmed within the limited calculation time, and thus, it happened that the limit time was reached and it was decided that the faulty lines were unrepairable before all the repairable combinations could be confirmed, or, even if all the faulty lines were repaired, a repair solution far from the optimum repair solution was presented (outputted) in some cases.
In particular, in case a faulty element exists in a spare line, the combination in application of the spare line is added, and further, in case a spare line can take charge of a plurality of memory array areas, the plurality of areas scramble for one spare line, so that, in such a case, the number of combinations further increases, and thus, it becomes harder to obtain the repair solution, which is a problem.
As mentioned above, recently semiconductor memories are being more and more enhanced in the density and architectural complication thereof, as a result of which, in case of using the conventional repair methods, the optional combination in line replacement by spare lines become huge in number, and thus, it takes much time for the calculation thereof, so that the cases where faults are unrepairable within the limited time are further increased, resulting in the lowering in productivity.
Further, even in case there is a repair solution, it was often decided that the faults could not be repaired. In particular, in case faulty elements exist in a spare line, the search for a repair solution became far more difficult, which was a problem.